1. Field of the Invention
This invention relates in general to digital signal processing systems for processing signal data obtained by converting information signals such as audio signals to digital data for an instance from PCM signals and control data used for the discrimination of the type of signal data, control data and so forth.
2. Description of the Prior Art
When recording and reproducing audio signals for music or the like in the form of PCM signals with the usual home video tape recorder, it is necessary to convert a PCM audio signal into a signal having a data format conforming to the television signal of a standard system such as the NTSC system.
As an example of the conversion into PCM signal, 2-channel stereophonic audio signals are individually sampled at a sampling frequency of about 44 kHz, and one sample data (i.e., one word) is converted into a 16- or 14-bit PCM digital data, which is placed in a video signal portion of a standard television signal. FIG. 1 shows an example of the data format of one horizontal scanning period (1 H period) for the case where one word is the 14-bit data form mentioned above. In the data block for 1 H shown in FIG. 1, six words of PCM signals for the left and right channels are alternately arranged, with two error correction words P and Q and one 16-bit error detection word CRC all of which constitute a 9-word 128-bit data block. The PCM data L and R shown in FIG. 1 respectively correspond to the left and right sampled data, and suffixes attached represent the sampling order. In the format of FIG. 1, the data is interleaved such that in each sampled data the six words and two error correction words P and Q, i.e., a total of eight words, are successively shifted by 16 blocks (i.e., 16 horizontal lines) for each word, and D in the aforementioned suffixes represents this number of blocks (D=16) of the interleave. In this case, the interleave of D=16 blocks is equivalent to a word interleave of 3D=48 words.
In FIG. 1, the period of one horizontal line (1H) is constituted of 168 bits. In this 168-bit interval, the horizontal sync signal HS which has 13 bits is placed, then a 4-bit clock signal CK for synchronization of data is placed after an interval of 13 bits, and then the aforementioned 128-bit data block is placed. The code of the data synchronization signal CK is, for instance, "1010." Also, after the 128-bit data block a "0" signal of one bit is placed, and then a white reference signal W with a pulse width of 4 bits is placed.
FIG. 2 shows a 1 H period in which a control signal data block is contained. This format is the same as that of FIG. 1 except for the 128-bit control data block, including the horizontal sync signal HS and white reference signal W. The 128-bit control data block in this case is constituted by a 56-bit heading signal word S, a 14-bit content discrimination signal word T, a 28-bit address signal word U, a 14-bit control signal word CT and the aforementioned 16-bit error detection word CRC.
The content of the 14-bit control signal word CT is set as shown in Table 1.
TABLE 1 ______________________________________ Control Bit Bit No. Code Content content content ______________________________________ 1 to 10 No prescription -- 0 11 Dubbing inhibition code Absent 0 12 p correction discrimination Present 0 code 13 Q correction discrimination Present 0 code 14 Pre-emphasis discrimination Present 0 code ______________________________________
In Table 1, the Q correction discrimination code is "0" representing the "presence" for the case when the word of the PCM audio signal is constituted by 14 bits, while where one word is constituted by 16 bits, for instance as in the data format shown in FIG. 3, the Q correction discrimination code is "1" representing "absence."
FIG. 3 shows an example of the data block in which one word by the PCM audio signal mentioned above is constituted of 16 bits. Here, an 8-word, 128-bit data block is constituted by six 16-bit words of the left and right channel audio signal data L and R, a 16-bit error correction word P and a 16-bit error detection word CRC, i.e., a total of eight words.
In this format, the error correction word Q is omitted, and only a single error correction word P is used. In this case, in order to provide for the compatibility with respect to the aforementioned 14-bit data format, it is desirable to subdivide the 16-bit data for one word into, for instance, a 14-bit portion and a 2-bit portion and thereby retain a 14-bit unit pattern. In the format of FIG. 3, for instance, the 14-bit portions of the respective seven words, namely the six audio signal data words L and R and one error correction word P, are placed in the same position as the individual corresponding words in FIG. 1, and the remaining 2-bit portions of these seven words are then arranged in the same order as 14-bit data in the position of the error correction word Q in FIG. 1. The other signal components in the 1-H period such as the horizontal sync signal HS and white reference signal W are in the same arrangement as in the format of FIG. 1.
In order to provide the compatibility for the format where one word consists of 14 bits and the format where one word consists of 16 bits, it is desired to provide the circuit with the compatibility and also permit one sampled data of analog audio signal to be encoded in 16 bits and converted into a 14-bit word through processing in the circuit.
The above data signals for 1 H unit are arranged in one vertical scanning period filed in a manner as shown, for instance, in FIGS. 4A and 4B. FIG. 4A corresponds to an odd field, and FIG. 4B corresponds to an even field. At the outset of each field, the equivalent pulse EP and vertical sync signal VS are arranged, the control signal block CDB is provided in the 10-th horizontal line in the odd field (see FIG. 4A) and in the 10.5-th horizontal line in the even field (see FIG. 4B), and then 245 horizontal lines with data block DB are provided, the remaining horizontal lines constituting a blank period BL.
Of the 262.5 horizontal lines constituting one field in FIGS. 4A and 4B, the 16.6 lines other than the 246 lines in which the aforementioned control signal block CDB and data block DB are provided correspond to the vertical blanking period of the standard television signal.